About Me
I’m a Postdoctoral Associate at the Research Laboratory of Electronics at Massachusetts Institute of Technology (MIT), advised by Prof. Anantha P. Chandrakasan. I received my Ph.D. (2024) and S.M. (2020) degree in Electrical Engineering and Computer Science from MIT, and B.S. (2018) degree in Electrical and Computer Engineering from Seoul National University.
I aim to design secure AI hardware while maintaining energy efficiency. Towards this goal, I work across computer architecture, where I develop tools that help designers navigate the trade-off between security and efficiency, and circuits, where I demonstrate effective defenses in silicon. My research is organized around three complimentary pillars towards secure and efficient AI hardware:
Develop Architectural Tools: I develop tools to model and predict security, energy, and performance trade-offs in AI hardware. These tools enable scalable and systematic exploration of the complex design space.
Design Efficient Defense Chips: I design and fabricate AI accelerator chips equipped with defense solutions. These silicon implementations actualize architectural insights into functional, efficient hardware.
Discover Threats: I identify attack surfaces emerging from performance optimizations in AI hardware. By combining novel algorithms with established hardware attack methods, I demonstrate high-impact threats compromizing integrity and privacy.
My Ph.D. thesis, titled “Towards Secure Machine Learning Acceleration: Threats and Defenses Across Algorithms, Architecture, and Circuits”, received MIT MTL Doctoral Dissertation Award (2024). My research has been recognized with the Siebel Scholars Award and the Best Student Paper Award from IEEE SiPS (2021) as well.